集成电路可测性设计IO复用方法  

Methods of DFT IO Multiplexing

作　　者：张玥[1] 万培元[1] 林平分[1] 

机构地区：[1]北京工业大学嵌入式系统实验室,北京100124

出　　处：《半导体技术》2011年第9期705-709,共5页Semiconductor Technology

基　　金：北京工业大学博士科研启动基金项目(X0000190110)

摘　　要：超大规模集成电路特征尺寸逐步缩小的发展过程中,芯片面积是制约芯片成本的最重要因素之一,也是直接影响半导体产品市场竞争力的最重要因素之一。本文介绍了将所有可测性设计(DFT)的输入输出端口(IO)与各种类型的正常功能工作模式的IO复用的方法,从而达到减少IO并最终减小芯片面积的目的。介绍了输入信号和输出信号分别在单向端口IO和双向端口IO中复用的方法。然后,以一款经过0.18μm逻辑工艺流片验证的flash存储器控制芯片为例,对比了采用IO复用方法前后芯片的利用率和面积,证明了方案的可行性和有效性。With the development of very large scale integration,whose feature si ze is shrinking gradually,chip area has become one of the most important factor s to affect the cost of one die,and finally affect the competitiveness of one s emiconductor product.The structures of multiplexing with all design for test（D FT） input/output ports（IO） and all types of normal working function IO were desc ribed to decrease the quantity of IO and ultimately achieve the goal of reducing area of the chip.The IO multiplexing methods of input signals and output signals in in put/output IO and bi-directional IO were introduced respectively.Takes a flash memory controller under 0.18 μm process for example,compare core utiliza tion and chip area before and after optimization by IO multiplexing.It proved t he feasibility and efficiency of scheme put forward was good.

关 键 词：面积 输入输出端口 复用 可测性设计 测试模式选择 

分 类 号：TN407[电子电信—微电子学与固体电子学]