一种改进的时钟网络设计方法及实现  

An Improved Clock Network Design Method and its Application

作　　者：鲍进威[1] 田丰[1] 喻小虎[1] 张建[1] 欧钢[1] 

机构地区：[1]国防科学技术大学卫星导航与定位中心,湖南长沙410073

出　　处：《全球定位系统》2011年第4期51-55,共5页Gnss World of China

摘　　要：针对自动时钟树综合和时钟网格+局部树这两种设计方法的优缺点,提出了一种结合两钟方式的改进的时钟设计方案—时钟网格+局部树自动综合(MLTAS),并将该方案应用于北斗二代用户系统的一款SOC芯片的设计中。在相同设计条件下,通过将该设计方案与自动综合的树形结构加以比较,结果显示:MLTAS比CTS可以实现更小的时钟偏差,同时可以降低缓冲器的数量。所以在高性能芯片设计中MLTAS比CTS更适合在时钟网络中的设计。According to the advantages and disadvantages of two design methods which are ClockMesh and ClockTree Synthesize, a improved design method that is constitute by them is proposed in this artical, which combine ClockMesh and LocalTree Auto Synthesize （MLTAS）. This method is implemented on a SOC chip which is used in the users＇ system of BD-2. Under the same conditions, compared results of MLTAS and auto synthesized tree structure, and it shows that the MLTAS is able to achieve smaller clock skew and fewer buffers than the auto synthesied methord, so MLTAS is more suitable for the high performance chip design than CTS in the clock network design.

关 键 词：时钟树综合 LMTAS 时钟偏差 缓冲器 

分 类 号：TN402[电子电信—微电子学与固体电子学]