基于FPGA的数字式抢答综合仪的设计与研究  

Design And Study of Digital Responder Synthesize Instruments Based on FPGA

作　　者：蒋炜华[1] 陈晓宇[1] 

机构地区：[1]河南机电高等专科学校,河南新乡453000

出　　处：《河南机电高等专科学校学报》2011年第3期12-14,共3页Journal of Henan Mechanical and Electrical Engineering College

摘　　要：传统的数字式抢答综合仪多数由单片机或集成数字芯片来实现,文中介绍了基于VHDL硬件描述语言进行数字式抢答综合仪设计的一般思路和方法。选择Altera公司低功耗、低成本、高性能的FPGA芯片,采用quar-tusⅡ8.1开发工具进行了程序的编译和功能仿真。最后给出了部分VHDL源程序和仿真结果,仿真结果表明该系统的设计方案正确。Digital Responder Synthesize Instruments is usually developed by micro processor or Integrated digital chip.This paper introduces the general design methods of Digital Responder Synthesize Instruments base on VHDL（hardware description language）.the FPGA chip of ALTERA Corporation was chosen with the low power loss,the low cost and the high performance,the Quartus Ⅱ8.1 development tools was used to compile and stimulate.Finally,The VHDL source programmer and simulating results are given.The simulating results show that the design method is correct.

关 键 词：VHDL FPGA 数字式抢答综合仪 仿真 

分 类 号：TN46[电子电信—微电子学与固体电子学]