H.264视频解码器中帧内预测模块的硬件设计  

Hardware design of intra prediction in H.264 video decoder

作　　者：宋健[1] 王祖强[1] 秦盼[1] 

机构地区：[1]山东大学信息科学与工程学院,山东济南250100

出　　处：《电子技术应用》2011年第10期53-55,59,共4页Application of Electronic Technique

摘　　要：提出一种能实时处理的H.264/AVC帧内预测硬件结构。通过对H.264/AVC各个预测模式的分析,设计了一个通用运算单元,提高了硬件资源的可重用性。采用4个并行运算单元计算预测值,对运算比较复杂的plane模式预处理,并设计模式预测器,加快了系统处理速度。硬件电路结构已通过RTL级仿真及综合,并在Altera公司的Cyclone Ⅱ FPGA平台上进行了验证和测试。A hardware architecture for real-time implementation of intra prediction is proposed. According to analyzing all intra prediction modes, this paper designs a processing element, the processing element improves the reusability of hardware resources. In order to improve the processing speed, four parallel processing elements are employed, plane mode precomputation and mode predictor are adopted. The intra prediction decoder has pass RTL level emulation and synthesis; it has verification and test on cyclone Ⅱ FPGA platform.

关 键 词：H.264 解码器 帧内预测 硬件 

分 类 号：TN919.8[电子电信—通信与信息系统]