SDRAM控制器简易化设计  

Simplied designing method for SDRAM controller

作　　者：刘浩淼[1] 卞树檀[1] 朱守保[1] 

机构地区：[1]第二炮兵工程学院,陕西西安710025

出　　处：《电子设计工程》2011年第19期52-54,60,共4页Electronic Design Engineering

摘　　要：SDRAM存储芯片拥有快速读写的性能,可以应用以回波模拟系统作为数据高速缓存器。SDRAM芯片是由SDRAM控制器控制的,SDRAM控制器有严格的控制时序和工作状态,可以使用有限状态机理论和VerilogHDL语言对FPGA进行模块化开发设计。笔者基于FPGA给出了一种SDRAM控制器简易化设计方法,实验结果表明该方法简化了SDRAM控制器的设计。SDRAM has fast reading and writing ability,it could be used as a data cach in echo simulation system.SDRAM is controlled by SDRAM controller. With strict time sequence and working states, SDRAM controller could accurately read or write data,which was developed and designed in the way of modularization,with finite state machine （FSM） theory and in VerilogHDL language on FPGA. Based on FPGA,the author put forward a easy design method of SDRAM controller. The result shows that this method simplifies the SDRAM controller design.

关 键 词：SDRAM控制器 FPGA 有限状态机 VERILOGHDL 

分 类 号：TP333.8[自动化与计算机技术—计算机系统结构]