可重构处理器阵列的系统级建模研究  

Research on Systme-Level Modeling of Reconfigurable Processor Array

作　　者：潘鹏[1] 王鹏[1] 林水生[1] 

机构地区：[1]电子科技大学通信与信息工程学院,四川成都611731

出　　处：《微电子学与计算机》2011年第11期85-88,93,共5页Microelectronics & Computer

摘　　要：由于粗粒度可重构体系结构设计空间复杂,设计满足应用需求的CGRA需要建立系统级仿真模型进行性能评估.文中提出一种可重构处理器阵列的系统级模型,使用SystemC事务级语言实现建模.模型采用多层互连网络结构实现任意2个处理器间的通信,并且处理器的资源能够通过参数快速地进行配置.仿真实验表明,模型适用于应用算法到粗粒度可重构体系结构映射的模拟仿真.Due to the complexity of coarse--grained reconfigurable architectures, design of CGRA require system-- level modeling and simulation--based performance exploration. This paper proposes a system--level model for reconfigurable processor array, which is constructed with SystemC transaction level language. The model is based on a hierarchical intercornect network, in which any two processors can initiate communication and resources in processors can be quickly configured by parameters. The result of the simulation shows that the model can be used in the simulation of application algorithms mapping onto CGRA.

关 键 词：粗粒度可重构体系结构 处理器阵列 SystemC事务级建模 

分 类 号：TP391.9[自动化与计算机技术—计算机应用技术]