LU分解在众核结构仿真器上的指令级调度研究  

Study on Instruction Scheduling of LU Decomposition on Many-core Architecture Simulator

作　　者：余磊[1,2] 刘志勇[1] 宋风龙[1,2] 叶笑春[1,2] 

机构地区：[1]中国科学院计算技术研究所,系统结构重点实验室,北京100190 [2]中国科学院研究生院,北京100039

出　　处：《系统仿真学报》2011年第12期2603-2610,共8页Journal of System Simulation

基　　金：国家“九七三”重点基础研究发展规划项目(2005CB321600);国家自然科学基金重点项目(60736012);国家自然科学基金(61070025);国家“八六三”高技术研究发展计划项目基金(2009AA01Z103);国家杰出青年科学基金(60925009);国际合作欧盟MULTICUBE项目(FP7-216693);北京市自然科学基金(4092044)

摘　　要：随着集成电路工艺的发展,众核处理器体系结构逐渐成为计算机体系结构设计者的研究热点。众核体系结构通过任务级的并行来提升整个处理器的性能。然而,指令级的并行性仍然是众核设计者需要认真考虑的问题。对浮点运算效率和加速比进行了形式化描述,验证了进行指令级调度的必要性。对处理器核内流水线进行详细分析,指出了指令级调度的一般性问题。提出了在众核结构上使用指令级调度和软件流水的方法。针对Splash2程序集里的LU分解算法,使用众核结构的硬件支持,在Scratched Pad Memory(SPM)上给出了调度指令的方案。在众核仿真器Godson-T上仿真了经过指令级调度后的算法,当使用64个线程处理512×512的矩阵时,程序性能达到调度前性能的4倍。With the development of the technology of integrated circuit,many-core architecture has become the research focus.The task level parallelism improves the performance of applications on many-core architecture.However,the instruction level parallelism is still the important issue that computer architectures designer must handle.The float efficiency and speedup were formalized and the necessity of instruction level scheduling was verified.The pipeline in the core was analyzed in details and the general problems of pipeline were pointed out.The instruction scheduling and software pipeline method were proposed.For the LU decomposition in Splash2,with the hardware support,the method on Scratched Pad Memory was simulated.The experiments show that the speedup can achieve 4 when the matrix is 512×512 and the number of threads is 64.

关 键 词：计算机体系结构 众核 加速比 指令级并行 LU分解 

分 类 号：TP301[自动化与计算机技术—计算机系统结构]