动态量化的LDPC译码器结构  

LDPC Decoder Architecture with Dynamic Quantization

作　　者：沈旭[1] 梁伟[1] 李婉[2] 叶凡[1] 任俊彦[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433 [2]南京邮电大学自动化学院,南京210046

出　　处：《计算机工程》2011年第21期232-234,237,共4页Computer Engineering

基　　金：国家科技重大专项基金资助项目"载波体制超宽带高速无线通信芯片研发与应用示范"(2009ZX03006-007-01);国家科技重大专项基金资助项目"超宽带设备的技术规范和性能评测"(2009ZX03006-009)

摘　　要：为降低低密度奇偶校验码(LDPC)译码器的复杂度,提出动态量化的LDPC译码器结构。针对传统并行结构,采用自适应动态量化算法、层调度策略以及最小和算法,在译码的同时调整信息量化方式,由此设计自适应估计电路,并统计幅值过大的信息比例。实验结果表明,该结构能以较小的性能损失降低LDPC译码器的复杂度。Self-adaptive dynamic quantization algorithm combined with level scheduling policy and min sum algorithm can decrease the hardware complexity of Low Density Parity Check Codes（LDPC） decoders with little performance degradation.To fill an omission of decoders using this algorithm,this paper proposed a new architecture of LDPC decoders.It is based on the traditional partial-parallel architecture,but can change the quantization scheme of decoding information.It also concludes circuits used to static the percentage of the value of information closing to saturation,which helps to adjust the quantization scheme of information in a self-adaptive way.Experimental results show that,this architecture can greatly reduce the hardware complexity of LDPC decoders with little performance degradation.

关 键 词：LDPC编码 量化 译码器 层调度策略 

分 类 号：TP301.6[自动化与计算机技术—计算机系统结构]