一种面向超标量处理器的高能效指令缓存路选择技术  

An Energy-Efficient Combining Way Selective Technique for the Instruction Cache in Superscalar Microprocessors

作　　者：谢子超[1] 陆俊林[1] 佟冬[1] 王箫音[1] 程旭[1] 

机构地区：[1]北京大学微处理器研究开发中心,北京100871

出　　处：《电子学报》2011年第11期2473-2479,共7页Acta Electronica Sinica

基　　金：国家"核高基"重大专项:安全适用计算机CPU研发与应用项目(No.2009ZX01029-001-002)

摘　　要：路选择技术可以有效降低指令缓存能耗开销,但已有方法通常会由于预测错误或更新机制复杂而引入额外的取指延迟,导致整体能效性降低.本文面向典型超标量处理器的指令缓存结构,提出了一种高能效的路选择融合技术(Combining Way Selective Cache,CWS-Cache).基于对路预测和路历史技术适用条件的分析,CWS-Cache在不同的取指场景中选择使用最佳路选择策略,有效降低了指令缓存的取指能耗,并通过缩短非对齐取指组的访问延迟提升处理器性能.实验表明,CWS-Cache将拥有8路组相联指令缓存的基础处理器取指能耗降低了84.98%,性能提升了3.50%.与已有的三种方法相比,CWS-Cache能效性分别提升了15.48%,14.13%和8.76%.Way selective technique could reduce the inslruction cache energy consumption significantly. However, existing solutions usually bring extra fetch latency due to mispredictions or complicated updating mechanism,reducing the energy-efficiency. The paper presents an energy-efficient Combining Way Selective Cache for the instruction cache in superscalar processors （CWS- Cache）. It combines the advantages of way prediction and way history techniques, and selects the best way selective mechanism for different situations. It not only reduces the inslruction fetch energy effectively, but also improves performance by reducing the laten- cy of misalignment fetch groups.Experimental results demonstrate that, on average, CWS-Cacbe reduces fetch energy consumption of the 8-way set-associative instruction cache in the baseline processor by 84.98 %, and improves performance by 3.5 %. Compared with three existing techniques,CWS-Cache improves the energy-delay product （EDP） by 15.48% ,14.13% ,and 8.76% ,respectively.

关 键 词：超标量处理器 路预测 路历史 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]