一种FPGA抗辐射工艺映射方法研究  

An FPGA Robust Technology Mapping Method

作　　者：陈志辉[1] 章淳[1] 王颖[1] 王伶俐[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《电子学报》2011年第11期2507-2512,共6页Acta Electronica Sinica

摘　　要：提出一种基于部分TMR和逻辑门掩盖的FPGA抗辐射工艺映射算法FDRMap,以及一个基于蒙特卡洛仿真的并行错误注入和仿真平台.该平台和算法已经应用到复旦大学自主研发的FPGA芯片FDP4软件流程的工艺映射模块.实验结果表明,FDRMap能够在增加14.06%LUT数目的前提下,降低电路的抗辐射关键度32.62%;与单纯采用部分TMR的方法相比,在节省12.23%的LUT数目同时,还能额外降低电路关键度12.44%.A novel radiation-hard FPGA technology mapping method based on partial TMR and logic gate masking and a fast parallel fault injection and Monte Carlo simulation platform are presented.This platform and method have been used in the mapping module which is part of the CAD flow for self-developed FPGA by Fudan University named FDP4.The experimental results show that FDRMap can decrease the circuit fault criticality by 32.62% with the 14.06% area penalty.Comparing to the partial TMR,it decreases the criticality by 12.44% along with reducing the resources by 12.23%.

关 键 词：现场可编程门阵列 工艺映射 抗辐射 错误仿真 单粒子翻转 

分 类 号：TN47[电子电信—微电子学与固体电子学]