基于SVM概率建模的硬件实现优化算法  

Optimized Algorithm for Hardware Implementation Based on SVM Probability Modeling

作　　者：杨镇西[1] 张丽[1] 聂智良[1] 

机构地区：[1]国家数字交换系统工程技术研究中心,郑州450002

出　　处：《计算机工程》2011年第23期217-219,共3页Computer Engineering

基　　金：国家"863"计划基金资助项目(2008AA011002)

摘　　要：在2种基于一对一分类策略的支持向量机(SVM)多类概率建模算法中,Pairwise Coupling概率建模算法不适合FPGA硬件实现,而投票概率建模算法分类性能较差。为此,提出一种基于Sigmoid函数的SVM概率建模的硬件实现优化算法,该算法基于合并计算及Log-add计算方法。理论分析结果表明,该算法可避免复杂的迭代计算和大量指数计算,减少运算量,并易于FPGA硬件实现。For the unsuitable Field Programmable Gate Array（FPGA） implementation of the Pairwise Coupling probability modeling and the poor classification performance of the voting probability modeling which are the two commonly used Support Vector Machine（SVM） probability modeling algorithms based on One Against One（OAO） classification strategy,an optimized algorithm for hardware implementation of probability modeling SVM is proposed which is based on Sigmoid function and Log-add with combined computation is proposed from the point of compromise.The theoretical analysis shows that this algorithm avoids complex iterative calculation and a large number of exponential calculations.It greatly reduces the amount of computation and is easy for FPGA implementation.

关 键 词：支持向量机 一对一分类 概率建模 SIGMOID函数 现场可编程门阵列 硬件实现 

分 类 号：TP301.6[自动化与计算机技术—计算机系统结构]