非线性延时模型及逻辑门优化设计  

A Nonlinear Gate Delay Model and Optimization of CMOS Logic

作　　者：秋小强[1,2] 杨海钢[1] 周发标[1,2] 谢元禄[1] 

机构地区：[1]中国科学院电子学研究所,北京100190 [2]中国科学院研究生院,北京100049

出　　处：《微电子学》2011年第6期901-905,共5页Microelectronics

基　　金：国家重大科学研究计划资助(2011CB933202)

摘　　要：为了解决信号斜率对逻辑门延时的影响,提出一种基于逻辑努力的非线性逻辑门延时模型。模型引入非线性修正因子,该修正因子通过对仿真数据的模拟,由优化算法求得。针对不同的连线负载,提出模型得到的延时与仿真得到的延时误差小于3%。仿真结果表明,在不同的连线负载下,采用该模型优化设计的译码器延时最小,验证了模型的有效性。A nonlinear gate delay model based on logic effort was proposed to reduce effects of input signal slope on gate delay.A nonlinear correction factor,which was obtained from simulation using optimization algorithm,was introduced into the model.The delay model was used in the design of decoders.It has been shown that the difference between simulated delay and calculated delay with the proposed model was less than 3% for different wiring loads.Simulation results indicated that the decoder optimized with the proposed model had the minimum delay for high load,which validated the effectiveness of the model.

关 键 词：延时模型 逻辑努力 信号斜率 逻辑门 粒子群算法 

分 类 号：TN47[电子电信—微电子学与固体电子学]