基于90nm低功耗NMOS工艺射频器件的版图优化  

Layout Optimization for RF Performance Enhancement in 90-nm Low-Power NMOS

作　　者：郑伟[1] 李文钧[1] 刘军[1] 孙玲玲[1] 

机构地区：[1]杭州电子科技大学射频电路与系统教育部重点实验室,杭州310018

出　　处：《电子器件》2011年第6期645-648,共4页Chinese Journal of Electron Devices

基　　金：国家自然科学基金项目(60806011)

摘　　要：从器件版图结构的布局布线出发,提出了射频器件性能增强的的方法。寄生电容,寄生电阻会明显弱化大尺寸器件的射频性能,通过多个小尺寸单元管子的并联,形成大尺寸器件,从版图的布局布线出发,减小寄生电容,寄生电阻,优化器件结构,提升射频性能。在总栅宽一定时,通过变换单元器件的栅指数与器件的并联数,寻找最佳组合。通过优化,功率增益截至频率提升约300 GHz。New layout approaches are proposed to improve the transistor radio frequency （RF） performance in 90-nm NMOS. This work specifically focuses on the impacts of wiring effect of multiple devices on the corresponding parasitic capacitances and resistances. The influence of external resistance becomes more pronounced for large-di- mensional RF transistors due to severe IR drop. By changing muhipler of device rather than varying number of gate finger to get large total width, gate resistive parasities can be reduced effectively, leading to improved maximum oscillation frequency fmax After optimization ,fmax experiment data showed a tremendous increase （ about 300 GHz） from the initial layout.

关 键 词：RF—MOSFET 版图 寄生成分 电流增益截止频率 功率增益截至频率 

分 类 号：TN432[电子电信—微电子学与固体电子学]