基于FPGA技术的多通道CRC校验系统  

Multi-Channel CRC Checking System Based on FPGA Technology

作　　者：李洪进[1,2] 邓世昆[1] 

机构地区：[1]云南大学信息学院,昆明650091 [2]遵义医学院医学信息工程系,遵义563000

出　　处：《计算机系统应用》2012年第1期144-147,共4页Computer Systems & Applications

摘　　要：CRC编码由于其简单的编码规则的在网络及存储等诸多场合得到广泛应用,随着现代存储和传输技术的发展,软件编码校验已难以满足Gbit级高速传输的需要。基于FPGA技术设计了一个采用多通道高度并行技术实现的高速循环冗余校验(CRC)系统。系统采用五个2Gbps校验通道并行工作的方式来达到10Gbps的数据吞吐率,系统实现采用VerilogHDL硬件描述语言设计,在QuartusII8.0平台上进行综合与布线,并将该处理单元封装为独立的IP核,并以Altera公司的EP2C20F484C6芯片为下载目标进行实现验证。综合结果表明,本设计可满足高速数据完整性检查的速率要求。CRC codes are widely used in networking and storage,and many other occasions due to its simple encoding rules.With the development of modern storage and transmission technologies,the check of software code has been difficult to meet the needs of high level transmission of Gbit.This paper has been achieved highly parallel cyclic redundancy check（CRC） system which based on FPGA technology to design a multi-channel high-speed technology.The design uses five parallel channels of 2Gbps check in order to achieve data throughput rate of 10Gbps.Each CRC channel compatible with 32-bit Ethernet standard.This design uses VerilogHDL for hardware description language,QuartusII8.0 for Integrated wiring,and packaging the processing unit into an independent IP core,then uses the Altera Corporation＇s EP2C20F484C6 chips as download target for verification.The results show that the design can meet the rate＇s requirements of high-speed data integrity checks.

关 键 词：循环冗余校验 FPGA 10Gbps以太网 伽罗瓦域 

分 类 号：TN911.22[电子电信—通信与信息系统]