基于FPGA的SDX总线与Wishbone总线接口设计  

The Design of SDX-bus and Wishbone-Bus Interface Based on FPGA

作　　者：刘娟[1] 张智鹏[1] 

机构地区：[1]西安电子科技大学电子工程学院,陕西西安710071

出　　处：《电子科技》2012年第1期65-68,共4页Electronic Science and Technology

摘　　要：针对机载信息采集系统可靠性、数据管理高效性以及硬件成本的需求,介绍了基于硬件描述语言Verilog HDL设计的SDX总线与Wishbone总线接口转化的设计与实现,并通过Modelsim进行功能仿真,在QuartusⅡ软件平台上综合,最终在Altera公司的CycloneⅢ系列FPGA上调试。实验证明了设计的可行性。Aiming at the requirement of reliability, high data management efficiency as well as hardware cost of the airborne information acquisition system, this article mainly introduces the interface conversion of Sdx-bus and Wishbone-bus. The implementation of the design is based on Verilog HDL Language. It is simulated on the Model- Sim software, synthesized on the Quartus platform and tested through FPGA from The Cyclone Ⅲ by Ahera company. The results show that the design is feasible.

关 键 词：VERILOG HDL SDX总线 WISHBONE总线 MODELSIM Quartus Ⅱ 

分 类 号：TP334.7[自动化与计算机技术—计算机系统结构]