板级高速传输总线链路层关键技术研究与实现  

Research and Design of Link Layer in Board-level High-speed Transportation Bus

作　　者：周宏伟[1] 陈超[1] 张丽霞[2] 张英[1] 李永进[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073 [2]湖南师范大学数学与计算机学院,湖南长沙410081

出　　处：《国防科技大学学报》2011年第6期55-60,共6页Journal of National University of Defense Technology

基　　金：国家自然科学基金资助项目(61003075);湖南师范大学青年基金资助项目(数100636);国家"核高基"重大专项"超高性能CPU新型架构研究"资助项目(2011ZX01028-001-001)

摘　　要：随着高性能服务器和超大规模计算机的发展,系统设计者对板上高速互连总线的要求越来越高,如何使芯片间的数据传输延迟更小,提高计算通信比是需要解决的重要问题。论文研究了近年来发展迅速的超传输总线和PCI Express总线的链路层的特点,在此基础上提出了一种64位高速总线链路层体系结构,并对其关键技术进行了研究,设计实现了一种能够每时钟周期对16位数据进行加解扰的加解扰器,以及能够纠正链路间最大5个时钟周期延迟偏斜的线间传输延迟偏斜纠正器,功能验证结果表明所提出的设计功能正确。With the development of the high performance servers and very large scale super computers, the requirement for board-level high-speed data transportation bus is higher than before. How to reduce the transfer delay between chips and improve the ratio of computation to communication is very important. In light of this, the characteristics of link layer in Hyper Transport and PCI Express buses which are very popular in recent years was studied. On the basis of this, link layer architecture for a 64- bit high-speed data transportation bus was proposed and some key technologies were researched. A 16-bit scrambler/descrambler, which can scramble or descramble a 16-bit data in one cycle, was designed. A lane-to-lane deskew logic, which can correct 5 cycles delay skews at most between two lanes, was also proposed. The verification results show that the function of our designs is correct.

关 键 词：板级 传输总线 链路层 加解扰 延迟偏斜纠正 

分 类 号：TP302.1[自动化与计算机技术—计算机系统结构]