Jitter analysis and modeling of a 10 Gbit/s SerDes CDR and jitter attenuation PLL  

作　　者：WANG Hui CHEN Ying-mei YI Lv-fan WEN Guan-guo 

机构地区：[1]Institute of RF- ＆ OE-ICs, Southeast University, Nanjing 210096, China [2]Zhongxing Telecom Equipment Corporation, Shenzhen 518055, China

出　　处：《The Journal of China Universities of Posts and Telecommunications》2011年第6期122-126,共5页中国邮电高校学报（英文版）

基　　金：supported by the National Natural Science Foundation of China (60976029);the Research Foundation of Zhongxing Telecom Equipment Corporation

摘　　要：Jitter analysis and a linear model is proposed in this paper which predicts the characteristics of serial-deserial （SerDes） clock and data recovery circuit, and the characteristics include jitter transfer, jitter tolerance and jitter generation are particularly analyzed. The simulation results of the clock data recovery （CDR） model show that the jitter specifications exceed the mask of ITU-T optical transport network （OTN） G.8251 recommendations. The whole systems are validated by 9.95-11.5 Gbit/s CDR and the jitter attenuation phase locked loops （PLL） circuits using TSMC 65 nm CMOS technology.Jitter analysis and a linear model is proposed in this paper which predicts the characteristics of serial-deserial （SerDes） clock and data recovery circuit, and the characteristics include jitter transfer, jitter tolerance and jitter generation are particularly analyzed. The simulation results of the clock data recovery （CDR） model show that the jitter specifications exceed the mask of ITU-T optical transport network （OTN） G.8251 recommendations. The whole systems are validated by 9.95-11.5 Gbit/s CDR and the jitter attenuation phase locked loops （PLL） circuits using TSMC 65 nm CMOS technology.

关 键 词：OTN SERDES JITTER CDR PLL 

分 类 号：TN6[电子电信—电路与系统] TP274[自动化与计算机技术—检测技术与自动化装置]