高性能64位并行前缀加法器全定制设计  

Full-custom design of high-performance 64-bit Parall-Prefix adder

作　　者：王仁平[1] 何明华[1] 魏榕山[1] 陈传东[1] 戴惠明[1] 

机构地区：[1]福州大学物理与信息工程学院,福建福州350108

出　　处：《福州大学学报（自然科学版）》2011年第6期862-867,共6页Journal of Fuzhou University(Natural Science Edition)

基　　金：福建省科技重大专项基金资助项目(2009HZ010002);福建省教育厅科研资助项目(JA09001);福建省自然科学基金资助项目(2009J05143)

摘　　要：基于64位基4的Kogge-Stone树算法原理,采用多米诺动态逻辑、时钟延迟多米诺和传输管逻辑等技术来设计和优化并行前缀加法器的结构,达到减少了加法器各级门的延迟时间目的.为实现版图面积小、性能好,采用启发式欧拉路径算法来确定块进位产生信号电路结构,采用多输出多米诺逻辑来优化块进位传播信号,采用6管传输管逻辑的半加器.该加法器全定制设计采用SMIC 0.18μm 1P4M CMOS工艺,版图面积为0.137 9mm2,在最坏情况下完成一次64位加法运算的时间为532.26 ps.A parall-prefix adder based on 64-bit radix-4 Kogge-Stone tree algorithm principle is proposed in this paper.The architecture is optimized using domino dynamic logic,clock delayed domino and transmission pipes logic,which reduces the gate delay of each stage in the adder dramatically.In order to achieve small layout area and good performance,heuristic Euler algorithm is adopted to determine the block carry generation signals circuit structure,multi-output domino logic is adopted to optimize the block carry propagate signals,and six transmission pipes logic is used to build a half-adder.Using SMIC 0.18 μm 1P4M CMOS process for layout design,the adder＇s area is 0.137 9mm2.In the worst case,the computation time is 532.26 ps.

关 键 词：并行前缀加法器 基4点操作 多米诺逻辑 欧拉路径算法 

分 类 号：TN02[电子电信—物理电子学]