基于Verilog的正则表达式编译器的实现  

Implementation of Regular Expression Compiler Based on Verilog

作　　者：邓凯元[1] 

机构地区：[1]北京信息科技大学光电信息与通信工程学院,北京100101

出　　处：《计算机系统应用》2012年第2期229-232,共4页Computer Systems & Applications

摘　　要：随着网络带宽的快速增长,正则表达式匹配逐渐成为网络数据处理系统的性能瓶颈。为了获得更高的匹配效率,基于FPGA的正则表达式匹配引擎成为近年来的研究热点之一,而将正则表达式高效的转换成硬件描述语言是其中的关键技术。首先分析了正则表达式转换为硬件电路的算法,然后在此算法基础上实现了一个编译器。最后在Modelsim平台上进行了仿真,仿真结果证明了编译器的正确性。With the rapid development of network bandwidth, regular expression matching is becoming the performance bottleneck of networking data processing system. For the purpose of achieving higher matching sPeed, regular expression matching engine based on FPGA has become one of the recent hot fields. And it is the critical technology how to efficiently transfer regular expression to hardware description language. In this paper, we first analyze the algorithm of converting regular expression to hardware circuit, and then implement a compiler based on this algorithm. Finally we simulate the circuit on the Modelsim platform. The results proved the accuracy of the compiler.

关 键 词：正则表达式 FPGA 模式匹配 VERILOG 

分 类 号：TP314[自动化与计算机技术—计算机软件与理论]