基于模型的安全比较核设计  

Model-Based Design of Safe Compare Core

作　　者：刘明端[1,2] 穆建成 马连川[2,4] 尚麟宇[2] 

机构地区：[1]北京交通大学轨道交通控制与安全国家重点实验室,北京100044 [2]北京交通大学电子信息工程学院,北京100044 [3]铁道部科技司,北京100844 [4]轨道交通运行控制系统国家工程研究中心,北京100044

出　　处：《沈阳建筑大学学报（自然科学版）》2011年第4期792-797,共6页Journal of Shenyang Jianzhu University：Natural Science

基　　金：国家科技支撑计划项目(2009BAG14B01);铁道部项目(2001X005-A)

摘　　要：目的研究安全比较核的结构,并应用于2乘2取2结构的安全系统.方法利用Simu-link和其相关工具对安全比较核进行建模与验证,使用Simulink HDL Coder对所建模型进行自动代码生成,将生成的代码和工程应用于Altera Cyclone II系列的EP2C5T144芯片进行实物测试,在FPGA上将其实现基于模型的设计.结果便于产品的修改和维护.设计过程不需要编写代码,相比于传统的设计方法节省了近50%的时间,有着更高的可靠性,并且在FPGA资源的消耗上减少了约10%.结论基于模型的设计方法在设计流程的任何阶段都可以对模型进行修改,而不会影响之前的工作,有着极高的效率.标准化的自动代码生成也保证了其可靠性.该设计方法有很强的应用价值.The purpose of this paper is to research the structure of safe compare core and implement it in FPGA by using the model-based design method.Safe compare core will be applied to the 2＊2-out-of 2 safe system.Safe compare core＇s model was created and verified by using Simulink HDL Coder and other related tools.Automatic code generation was implemented by Simulink HDL Coder,and the code was applied to the Altera Cyclone II EP2C5T144.The results show that this method of model-based design is good for project＇s modification and maintenance.As there is no need to write code,this method can save nearly 50% of the time with a higher reliability.In addition,FPGA resource consumption was reduced by about 10%.Therefore,the model can be modified by the model-based design at any stage in the design flow,and the method has a high efficiency because of that.Standardized automatic code generation also ensures the project＇s reliability rate.This design method has a strong application value.

关 键 词：SIMULINK HDL CODER FPGA 2乘2取2 安全比较核 

分 类 号：TP309.1[自动化与计算机技术—计算机系统结构]