引入SRAM的三级缓存技术在高速通信中的应用  

Tri-stage buffer used in the high-speed communication by the addition of SRAM

作　　者：史赟[1] 郑永秋[1] 任勇峰[1] 

机构地区：[1]中北大学电子测试技术国家重点实验室,山西太原030051

出　　处：《重庆邮电大学学报（自然科学版）》2012年第1期60-63,95,共5页Journal of Chongqing University of Posts and Telecommunications(Natural Science Edition)

基　　金：国家自然科学基金(60871041)~~

摘　　要：在高速通信过程中,数据处理系统通常需要数据缓存来实时存储收到的数据。利用现场可编程门阵列(field programmable gate array,FPGA)内部资源构建的先进先出(first in first out,FIFO),其容量有限,在数据通信过程中由于读写速度不匹配而导致FIFO溢出,从而出现丢数现象。为此设计并实现了一种三级缓存结构,在FPGA外部引入1 MByte容量的静态随机存储器(static random access memory,SRAM)作为中间级缓存,输入级和输出级缓存为FPGA内部的FIFO,FPGA控制数据的传输和对SRAM的读写操作。采用三级缓存技术,简化了硬件复杂度,提高了设计的可实现性,经多次测试表明,本技术稳定可靠。In the high-speed communication,data process system usually needs data buffer to store data timely.The FIFO which is structured by using the internal resources of field programmable gate array（FPGA） has limited capacity,which easily leads to the overflow of FIFO and data discarded,if the speed of reading does not match the speed of writing.To resolve this problem,this paper designs and realizes tri-stage buffer.A SRAM whose capacity is 1MB is added to the exterior of FPGA as the middle buffer.The input buffer and output buffer are the FIFO of FPGA,and FPGA controls the data transmission and the writing and reading operation of the SRAM.Adopting tri-stage buffer technique simplifys the complexity of the hardware and increases the reachability of the design.Tests show that tri-stage buffer technique is reliable and steady.

关 键 词：三级缓存 静态随机存储器 先进先出(FIFO) 现场可编程门阵列(FPGA) 

分 类 号：TN784[电子电信—电路与系统]