FT-SIMD:一种高性能乘法器的设计  

FT-SIMD: Design of a High-Performance Multiplier

作　　者：李国强[1] 陈书明[1] 万江华[1] 杨惠[1] 

机构地区：[1]国防科学技术大学计算机学院,湖南长沙410073

出　　处：《计算机工程与科学》2012年第1期53-57,共5页Computer Engineering & Science

基　　金：核高基重大专项(2009ZX01034-001-006)

摘　　要：为了提高多媒体数据的处理能力,高性能DSP普遍引入了SIMD技术。作为DSP重要组成部分的乘法器也必须具备这一功能。本文对SIMD乘法器的实现进行深入研究,提出了一种新的SIMD乘法器体系结构,采用两个16×8乘法器,通过对其操作数和结果进行符号扩展和拼接等处理,简单而高效地实现了16位FT-SIMD乘法器。同时,本体系结构可以扩展为32位和64位的SIMD乘法器。In order to enhance the multimedia data processing abilities, high performance DSPs have generally introduced the SIMD technology. As an important component in DSPs, the multiplier has to support the SIMD function. After an in-depth study on the SIMD multiplier＇s implementation, this work proposes a simple and highly effective 16 bit FT-SIMD multiplier, which is composed of two 16×8 bits multipliers, with the help of signed-expansion and splicing operations on the operands and results, the 16-bit SIMD multiply is effectively supported. What’s more, our multiplier can be easily expanded to support the 32-bit and 64-bit SIMD multiply operations.

关 键 词：SIMD 乘法器 5-2压缩 4-2压缩 BOOTH编码 

分 类 号：TP332.2[自动化与计算机技术—计算机系统结构]