可重构GrΦstl设计研究及其FPGA实现  

Research of reconfigurable GrΦstl algorithm on FPGA platform

作　　者：李志灿[1] 王奕[1,2,3] 李仁发[1,2,3] 

机构地区：[1]湖南大学嵌入式系统与网络实验室,长沙410082 [2]湖南大学湖南省研究生培养创新基地,长沙410082 [3]湖南大学网络与信息安全湖南省重点实验室,长沙410082

出　　处：《计算机工程与应用》2012年第6期49-52,共4页Computer Engineering and Applications

基　　金：国家自然科学基金(No.60873074);国家工信部核高基项目;中央高校基本科研业务费资助

摘　　要：GrΦstl是继承MD迭代结构和沿用AES压缩函数的SHA-3候选算法。目前的研究只针对GrΦstl算法的一种或两种参数版本进行实现,并没有针对GrΦstl四种参数版本的设计,缺少灵活性。在分析GrΦstl算法的基础上,采用可重构的设计思想,在FPGA上实现了GrΦstl四种参数版本。实验结果表明,在Xilinx Virtex-5 FPGA平台上,四参数可重构方案的面积为4279 slices,时钟频率为223.32 MHz,与已有的实现方法相比,具有面积小、时钟频率高及灵活性等优点。Grostl algorithm is one of SHA-3 finalist which is mainly composed of Message Digest （MD） iteration and AES compression function. Previous research work has been done on hardware implementation of Grostl algorithm, but the disadvantage of their implementation lies on only focusing on one or two parameters version of Grcstl and less flexibility. Base on the analysis of Grostl algorithm, this paper proposes a new reconfigurable architecture which can support four different parameters of Grostl algorithms. The proposed design ports to Xilinx Virtex-5 FPGA platform and achieved 223.32 MHz clock frequency using 4 279 slices. The experimental results show that the proposed design has smaller size, higher clock frequency and more flexibility supporting compared with the exist ng work when ports to FPGA platform.

关 键 词：安全散列算法(SHA) 可重构 现场可编程门阵列(FPGA) GrΦstl算法 

分 类 号：TP332.1[自动化与计算机技术—计算机系统结构]