pMOSFET中栅控产生电流的衬底偏压影响研究  

Effect of Substrate Bias on the Gate-controlled Generation Current in the pMOSFET's

作　　者：陈海峰[1] 过立新[1] 杜慧敏[1] 

机构地区：[1]西安邮电学院电子工程学院,西安710121

出　　处：《固体电子学研究与进展》2012年第1期10-13,共4页Research & Progress of SSE

基　　金：陕西省教育厅专项科研基金项目(11JK0902);西安市应用材料创新基金项目(XA-AM-201012);西安邮电学院青年教师科研基金项目(ZL2010-19)

摘　　要：研究了pMOSFET中栅控产生电流(GD)的衬底偏压特性。衬底施加负偏压后,GD电流峰值变小;衬底加正向偏压后,GD电流峰值增大。这归因于衬底偏压VB调制了MOSFET的栅控产生电流中最大产生率,并求出了衬底偏压作用系数为0.3。考虑VB对漏PN结的作用,建立了包含衬底偏压的产生电流模型。基于该模型的深入分析,很好地解释了衬底负偏压比衬底正偏压对产生电流的影响大的实验结果。The effect of substrate bias on the gated-diode generation （GD） current has been studied. The peak of GD current curve IGD,P decreases as the substrate bias VB becomes negative. However, IGD,pincreases as VB becomes positive. This ascribes that VB modulates the maximum generation rate of GD current. The factor of VB influencing on GD current is 0. 3. Based on the influence of VB on GD current, a GD current referring VB is set up. The model explains that negative VB has more influence on the GD current than the positive VB.

关 键 词：产生电流 衬底偏压 平带电压 p沟道金属氧化物半导体场效应晶体管 

分 类 号：TN386.1[电子电信—物理电子学]