FPGA比较矩阵排序法及在中值滤波器中的应用  

A FPGA Matrix Comparison Sort Algorithm and Its Application in Median Filter

作　　者：吕伟新[1] 李清清[1] 娄俊岭[1] 

机构地区：[1]哈尔滨工业大学机器人研究所,哈尔滨150001

出　　处：《电子器件》2012年第1期34-38,共5页Chinese Journal of Electron Devices

基　　金：国家自然科学基金项目(61075081)

摘　　要：排序运算广泛应用在数字图像处理等实时性要求较高场合,硬件实现排序运算可提高逻辑运算速度。采用大规模集成电路构造一种硬件矩阵比较器,将输入数据按行列排列后进行比较,使第j行的比较输出结果相加,即可求取第j个输入数据在输入数据集合中的序列值。采用FPGA芯片构造多种排序器,最大延时均在几十ns量级,将排序器应用于构造一维和二维中值滤波器延时小于50ns。硬件矩阵比较器实现排序和滤波,原理简单,实时性好。Sort algorithm is widely used in digital image processing. Hardware implementation can bring magnitude computing speed improvement. A sort algorithm is proposed, which distributes the input data in rows and columns constituting matrix comparator, the successive value of input data No. j in a collection is the sum of comparison values of row No. j. Several sorters are constructed with FPGA based on the matrix comparison sort algorithm,and the maximum delay is in the tens of nanoseconds. The delay of I-D and 2-D median filters,which are constructed by matrix comparator sort algorithm is less than 50ns. The matrix comparator sort algorithm is real time and simple in principle.

关 键 词：排序 比较矩阵排序 中值滤波 FPGA 

分 类 号：TP391.41[自动化与计算机技术—计算机应用技术]