数字HDTV信源解码器的硬件实现  

The Hardware Implementation of Digital HDTV Source Decoder

作　　者：王承宁[1] 俞斯乐[1] 李华[1] 国澄明 

机构地区：[1]天津大学电视与图像信息研究所,天津300072

出　　处：《电子学报》2000年第1期39-41,共3页Acta Electronica Sinica

基　　金：国家数字高清晰度电视重大科技产业工程项目资助课题

摘　　要：本文提出了一种主要基于ＦＰＧＡ的数字ＨＤＴＶ信源解码器的总体设计方案和硬件实现方法．同时还介绍了整机的测试系统和测试结果．目前，该信源解码器已研制完成，并参加了于１９９８年９月８日至１１日在北京成功进行了我国ＨＤＴＶ功能样机系统的公开演示．In this paper, the overall scheme and hardware implementation of a digital HDTV source decoder based on FPGA are Presented, and the test system and test results are described too. Now, the HDTV scarce decoder has been completely achieved. It took Part in the Chinese HDTV Function Prototype System demo Presented successfully in Beijing from Sept & to 11 this year.

关 键 词：HDTV 信源 解码器 FPGA MPEG-2 

分 类 号：TN949.17[电子电信—信号与信息处理]