高速并行LDPC编码的FPGA实现  

FPGA Implementation of High-speed Parallel LDPC Encoding

作　　者：叶荣润 黄聪 俞帆 

机构地区：[1]上海航天电子技术研究所,上海201109

出　　处：《无线电工程》2012年第3期25-26,37,共3页Radio Engineering

摘　　要：LDPC码具有优异的误码性能,并被很多协议采用,其中CCSDS规范就采用了LDPC码。符合CCSDS规范的LDPC码编码器的设计目的是满足卫星实际应用的需求,降低卫星信道传输的误码率。实现了8位并行LDPC码编码,并优化了矩阵信息的存储设计。在XC2V3000 FPGA实测中,8位并行编码吞吐量达到800 Mbps。Because of its excellent capability,LDPC codes have been adopted by many protocols such as CCSDS.The LDPC encoder conforming to CCSDS is investigated for satellite applications to reduce the BER of satellite channel transmission,8-bit parallel LDPC encoding is implemented,and the matrix information storage design is optimized.It is discussed that how to store the information of generator matrix of（8 176,7 154）LDPC codes.And the throughput of 8-bit parallel encoding exceeds 800Mbps on XC2V3000 FPGA.

关 键 词：低密度奇偶校验码 生成矩阵 CCSDS 矩阵存储 

分 类 号：TN911.22[电子电信—通信与信息系统]