高性能维特比在卫星导航接收机中FPGA实现  

Implementation of high-performance FPGA based Viterbi decoder in receiver for satellite navigation

作　　者：王千喜[1] 李秋凤[1] 杨晓昆[1] 翟羽佳[1] 胡强[1] 

机构地区：[1]中国航天科工信息技术研究院总体部,北京100070

出　　处：《现代电子技术》2012年第6期107-110,共4页Modern Electronics Technique

摘　　要：卫星定位接收机中卷积码译码即维特比译码器,在处理器中面临占有资源较多、处理时间过长等问题,为了减少处理器资源的占用和提高处理速度,采用并行加比选蝶形单元的的方法,在FPGA平台上用硬件描述语言设计一种高性能维特比译码器,作为GPS L2频点和GALILEO E1频点接收机的通用译码器,在GPS和GALILEO接收机上运用,大大减少资源使用,提高接收机的处理速度。The existing convolutinal code decoder-Viterbi decoder in satellite position receiverbe is confronted with the problems of multi-resource occupation and long time processing. A method of using parallel plus selection butterfly unit is a- dopted to reduce the ocupation of processer resource and increase the processing speecd. A high-performance Viterbi decoder was designed with hardware description language on the FPGA platform. It works on GPS and GALILEO receiver as a general decoder of GPS L2 and Galileo E1 frequency point receiver, and can reduce the resource occupation and improve the processing soeed of receivers.

关 键 词：VITERBI译码器 GPS/GALILEO接收机 卷积码 FPGA 

分 类 号：TN764-34[电子电信—电路与系统]