基于FPGA的SM3算法优化设计与实现  

Optimization Design and Implementation of SM3 Algorithm Based on FPGA

作　　者：王晓燕[1] 杨先文[2] 

机构地区：[1]河南中医学院学生工作部,郑州450008 [2]解放军信息工程大学电子技术学院,郑州450004

出　　处：《计算机工程》2012年第6期244-246,共3页Computer Engineering

基　　金：现代通信国家重点实验室基金资助项目(9140C1106021006);郑州市科技创新型科技人才队伍建设工程基金资助项目(096SYJH21099)

摘　　要：介绍SM3密码杂凑算法的基本流程,基于现场可编程门阵列(FPGA)平台,设计SM3算法IP核的整体架构,对关键逻辑进行优化设计。选用Cyclone系列器件作为目标器件,与现有算法进行实现比较,结果表明SM3算法IP核耗费较少的逻辑单元和存储单元,具有最高的算法效率,可为密码片上系统产品的开发提供算法引擎支持。Aiming at SM3 cryptographic Hash algorithm released by state cryptography administration, the general working flow of the algorithm is summarized in this paper. Based on Field Programmable Gate Array（FPGA） platform, the IP architecture of the SM3 is proposed, and the optimization design of its relevant crucial path is discussed. Choosing three Cyclone FPGAs of Altera corporation as the target devices, the fast implementation of the SM3 is achieved and is compared with some other existing research fruits. Comparison results indicate that the IP implementation of the SM3 consumes smaller logic element and memory bit but has higher algorithm performance. It can provide the algorithm engine for the development of cryptography System on Chip（SoC） products in practice.

关 键 词：密码杂凑算法 片上系统 关键路径 IP核 现场可编程门阵列 

分 类 号：TP309.1[自动化与计算机技术—计算机系统结构]