基于RISC的16位嵌入式CPU的设计  

Design of a 16-b Embedded RISC CPU and Its Implementation

作　　者：何寅[1] 陈旭昀[1] 杜晓刚[1] 周汀 程君侠[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点试验室,上海200433

出　　处：《微电子学》2000年第1期17-21,共5页Microelectronics

摘　　要：介绍了一个嵌入式RISC型CPU。该CPU采用哈佛结构、4级指令流水线、20位指令字长和16位数据字长,并设置了用于片内外部寄存器的高速接口。设计中采用Bypass技术解决了数据相关问题,开发了高效的结构化编程语言和相应的编译器。An embedded RISC CPU is presented,which has the Havard structure,4 stage pipeline,20 b instruction,and 16 b data.It specifies a high speed interface for registers in the chip.The problem of data impact is solved by using the bypass structure.An effective programming language and its corresponding compiler are developed ,which combines the advantages of assemble language and high level language.The RISC CPU is used in MPEG2 video decoder to control the bitstreams,distribute the original compressed data into several streams,and control the VLD decoder and other system level modules.

关 键 词：专用集成电路 嵌入式 RISC CPU 设计 

分 类 号：TP332.02[自动化与计算机技术—计算机系统结构]