一种考虑硅通孔电阻-电容效应的三维互连线模型  

Through-silicon-via-aware interconnect prediction model for 3D integrated circuirt

作　　者：钱利波[1] 朱樟明[1] 杨银堂[1] 

机构地区：[1]西安电子科技大学微电子学院,西安710071

出　　处：《物理学报》2012年第6期453-459,共7页Acta Physica Sinica

基　　金：国家自然科学基金(批准号:60725415;60676009);国家科技重大专项(批准号:2009ZX01034-002-001-005)资助的课题~~

摘　　要：硅通孔(TSV)是三维集成电路的一种主流技术.基于TSV寄生参数提取模型,对不同物理尺寸的TSV电阻-电容(RC)参数进行提取,采用Q3D仿真结果验证了模型精度.分析TSV RC效应对片上系统的性能及功耗影响,推导了插入缓冲器的三维互连线延时与功耗的解析模型.在45 nm互补金属氧化物半导体工艺下,对不同规模的互连电路进行了比较分析.模拟结果显示,TSV RC效应导致互连延时平均增加10%,互连功耗密度平均提高21%;电路规模越小,TSV影响愈加显著.在三维片上系统前端设计中,包含TSV寄生参数的互连模型将有助于设计者更加精确地预测片上互连性能.Through-silicon-via（TSV） is one of the major design techniques in three- dimensional integrated circuit（3D IC）.Based on the parasitic parameter extraction model,the parasitic resistance-capacitance（RC） parameters for different size TSVs are acquired and validated with Q3D simulation data.Using the results of this model,closed-form delay and power consumption expressions for buffered interconnect used in 3D IC are presented.Comparative results with 3D net without TSV in various cases show that TSV RC effect has a huge influence on delay and power of 3D IC,which leads maximum delay and power comsumption to extra increase 10% and 21%on average,respectively.It is crucial to correctly establish a TSV-aware 3D interconnect model in 3D IC front-end design.

关 键 词：三维集成 硅通孔 互连延时 功耗 

分 类 号：TN40[电子电信—微电子学与固体电子学]