数字时钟锁相环的设计与实现  

Designing and Implementing of Delay-Locked Loop

作　　者：裴志强[1] 杨玉飞[1] 刘宝娟[1] 

机构地区：[1]中国电子科技集团公司第四十七研究所,沈阳110032

出　　处：《微处理机》2012年第1期4-6,11,共4页Microprocessors

摘　　要：数字锁相环电路已在数字通信、无线电电子学及电力系统自动化等领域中得到了极为广泛的应用。在高密度可编程逻辑器件(FPGA)中,根据实际要求,设计FPGA专用数字锁相环电路,可充分利用器件资源,同时把一些相关的数字电路组合在一起,不仅提高了系统的集成度和可靠性,降低了功耗,降低了成本,而且可以使电路性能得到明显改善。Delay-Locked Loop（DLL） has already got the extremely application in some fields,such as digital communication technology,wireless electronics and electric power automation system etc..In according to actual condition,we may design special FPGA delay locked loop circuit in high density programmable logic device（FPGA）.we can make use of device resources and combination some related digital electric circuits together.We not only raise the system integrate and credibility,lower consume and cost,but also make the electric circuit function get the obvious improvement.

关 键 词：现场可编程门阵列 模拟锁相环 数字锁相环 

分 类 号：TN492[电子电信—微电子学与固体电子学]