布线约束下的低功耗扫描测试  

Routing-constrained low power scan test

作　　者：黄宁[1] 朱恩[1] 刘文松[1] 林叶[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《东南大学学报（自然科学版）》2012年第2期239-243,共5页Journal of Southeast University：Natural Science Edition

基　　金：国家高技术研究发展计划(863计划)资助项目(2009AA11Z219)

摘　　要：分析了扫描测试过程中功耗产生的原因,研究了扫描触发器跳变对内部组合逻辑锥的影响,并对其进行建模,将计算得到的影响函数值作为扫描链重排序的依据.然后,基于扫描链结构的特殊性,分析了布线约束对扫描链重新排序的影响,并将布线约束简化,提出了一种同时兼顾低功耗和布线约束的算法.该算法不需要迭代,通过一次运行即可得到扫描链重排序的结果,在保证后端设计可行性的前提下,尽可能减少了高影响值扫描单元上的跳变次数,实现了对扫描测试功耗的优化.基于电路测试算例以及ISCAS89基准电路集中的电路s298和s5378,进行了仿真实验,结果表明:所提算法可以使扫描测试功耗降低12%,对故障覆盖率以及测试时间没有任何影响,而且不需要任何硬件开销,可应用于芯片的量产测试.The causes of the power consumption during the scan test are analyzed. The effects of the scan flip-top＇s transitions on the internal combinational logic cone are studied and modeled. The cal- culated values of the influence function are used as the basis for the scan chain reordering. Then, the effects of the routing constraints on the scan chain reordering are analyzed based on the special scan chain structure. With the simplification of the routing constraints, an algorithm taking both low pow- er consumption and routing constraints into account is presented. This algorithm can get rid of itera- tions and obtain the result of the scan chain reordering by a single run. The transition times of the scan cells can be reduced with the high impact value under the premise of the feasible back-end de- sign, improving the scan test power consumption. The simulation experiments are performed on the test case and the circuits s298 and s5378 in the ISCAS89 benchmark circuits. The results show that this algorithm can reduce the scan test power by 12% without any effect on fault coverage and test time. Moreover, it does not require any hardware overhead and can be used for silicon production test.

关 键 词：扫描链 逻辑锥 低功耗 布线约束 重排序 

分 类 号：TN407[电子电信—微电子学与固体电子学]