一种精简的高速率功率MOS驱动器  

High-speed gate driver with a simple structure for power MOSFET

作　　者：何惠森[1,2] 来新泉[1,2] 许文丹[3] 赵永瑞[1,2] 田磊[4] 杜含笑[1,2] 

机构地区：[1]西安电子科技大学电路CAD研究所,陕西西安710071 [2]西安电子科技大学超高速电路设计与电磁兼容教育部重点实验室,陕西西安710071 [3]西安航空技术高等专科学校图书馆,陕西西安710071 [4]西安邮电学院电子工程学院,陕西西安710121

出　　处：《西安电子科技大学学报》2012年第2期168-174,共7页Journal of Xidian University

基　　金：国家自然科学基金资助项目(60876023)

摘　　要：设计了一种具有新颖的死区产生方法的高压功率MOS驱动电路,利用电阻调节驱动MOS管栅极电容充放电的时延,来产生极短的死区时间,可精简电路结构,提高驱动速率,并且无需电流偏置,就能有效降低电流源噪声.基于0.4μm BCD工艺,经Cadence环境下进行仿真验证.结果表明,该驱动电路能够产生10ns以下的死区时间,且传输时延低于70ns.对采用该驱动电路的一款功率因数校正芯片进行测试,驱动输出开关信号的上升沿时间为90ns,下降沿时间为55ns.功率因数可达0.995,总谐波失真为6.5%.A novel gate driver with a low transmission delay and ultra-low dead-time is proposed for driving power MOSFET.It controls the charge time and discharge time of the gate capacitor for minimizing dead-time,and no extra current bias and logic circuits are required,so it can simplify the driver circuit and reduce the noise in the current bias.Based on the 0.4 μm BCD process,the simulation is done in the Cadence environment,with good performance observed where the dead-time is below 10 ns and the transmission delay is below 70 ns.Then a Power Factor Correction（PFC） IC which utilizes this gate driver is tested for validation,and the test results indicate that the trise and tfall are 90 ns and 55 ns respectively that the power factor is 0.995,and that the Total Harmonic Distortion（THD） is as low as 6.5%.

关 键 词：驱动电路 功率MOSFET 功率因数校正 BCD工艺 死区时间 

分 类 号：TN386[电子电信—物理电子学]