同步降压DC-DC转换器驱动级设计  

Design of Gate Driver for Synchronous Step-Down Converter

作　　者：刘焱[1] 龚志鹏[1] 鲍小亮[1] 周泽坤[1] 张波[1] 

机构地区：[1]电子科技大学电子薄膜国家重点实验室,成都610054

出　　处：《微电子学》2012年第2期187-190,194,共5页Microelectronics

摘　　要：提出一种输入电压为4.5～23V、输出电流可达3A的同步降压转换器的驱动级,内部集成了电平移位、死区时间控制及同步管反向电流限制等功能。设计了一种为内部逻辑供电的低压电源,使驱动级大部分可以由低压器件构成,与外部电源供电的驱动级相比,大大减小了芯片面积。分析了该电路的结构与工作原理;采用0.6μm BCD工艺,通过HSPICE进行仿真,证明该驱动级方案切实可行。A gate driver was designed for synchronous step-down DC/DC converter,which could deliver up to 3 A output current from 4.5 V to 23 V input supply.Level shifter,adverse current limit of low side power MOSFETs and dead time control modules were incorporated into the circuit.Low-voltage power supply was designed for internal logic modules,so that the driver could be constructed mostly with low voltage devices.Compared with external supply powered driver,the proposed circuit occupies a much smaller chip area.Circuit structure and its operational principle were analyzed.HSPICE simulation based on 0.6 μm BCD process validated design of the gate driver.

关 键 词：同步降压 DC-DC转换器 电平位移 死区时间 LDO 

分 类 号：TN433[电子电信—微电子学与固体电子学]