一种基于GALS的四核内部互连及任务调度研究  

A GALS-Based Quad-Core Interconnection and Task Scheduling Mechanism Research

作　　者：杨栅[1] 蒋剑飞[1] 王琴[1] 

机构地区：[1]上海交通大学微电子学院,上海200240

出　　处：《微电子学与计算机》2012年第5期20-23,28,共5页Microelectronics & Computer

基　　金：国家"八六三"计划项目(2009AA011705)

摘　　要：本文给出一种基于全局异步局部同步(Global Asynchronous Local Synchronous)的四核数字信号处理器(Digital Signal Processor)内部互联设计方案.全局异步局部同步的设计模式可以使四个DSP核心根据任务需要工作在不同的频率域,从而降低芯片的总功耗且避免了全局时钟树设计.多核之间采用DMA通道进行数据交换,在占用较小CPU负担的同时,获得较大数据带宽.本文给出一种任务队列的任务调度机制,用于完成多核之间任务的自助申请调度以及数据流的控制.以MP3的解码程序为例,对任务在多核上的分割方法和调度策略进行详细的阐述.This paper presents a Quad-core digital signal processor design based on GALS （Global Asynchronous Local Synchronous） and interconnected with two DMA channels. GALS based design guarantees each core could work in different frequency domains according to the task request, thus the chip＇s total power consumption can be reduced and eliminate the difficulties on the constrains of the global clocks. Intercommunication with DMA channels between each core achieves high efficiency of data transmission with less processor load. A task scheduling mechanism based on the data flow is proposed to manage the tasks on each core which improves the efficiency of the processor and a MP3 decoder program is implemented on this processor to elaborate the task partition and schedule of the tasks and show the performance of the processor.

关 键 词：多核处理器 GALS多媒体 任务队列 任务调度机制 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]