一种低功耗高效率的AHB-AXI双总线结构联合Cache的IP设计  

A Low Power High Efficiency Unified Cache IP Design with AHB-AXI Bus Interface

作　　者：朱伟成[1] 周莉[1] 喻庆东[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《微电子学与计算机》2012年第5期46-49,53,共5页Microelectronics & Computer

基　　金：国家"八六三"重点项目(2009AA011700)

摘　　要：Cache作为处理器和系统总线之间的桥梁,是芯片功耗的主要来源,低功耗Cache设计在嵌入式芯片设计中具有重要意义.传统Cache设计一般依赖于特定体系结构,难以在不同的系统中进行集成,通用性差.本文提出了一种低功耗高效率的AHB-AXI双总线结构联合Cache的IP设计.实验结果显示,本设计可以显著降低Cache功耗和提高系统性能.As the bridge between CPU and system bus, Cache is the major power consumption source of the chip. Power efficient cache design is of great importance. And traditional cache design is lack of flexibility to integrate into different systems. A low power AHB-AXI double bus unified Cache design is proposed to reduce Cache access times and improve off-chip memory access efficiency. The test result shows that the design can notably reduce cache power consumption and improve system overall performance.

关 键 词：CACHE AMBA总线 自适应加载策略 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]