基于FPGA的高速雷达信号实时处理  

High-speed Real-time Radar Signal Processing Based on FPGA

作　　者：李若铭[1] 杨唐胜[1] 柯仙胜 

机构地区：[1]湖南大学电气与信息工程学院,长沙410082 [2]上海皮赛电子有限公司,上海200120

出　　处：《世界科技研究与发展》2012年第2期233-236,共4页World Sci-Tech R&D

基　　金：国家重大仪器专项(20827006)资助

摘　　要：介绍了一种实现高速雷达信号实时处理的IP核的实现方法。将采样率为4 G/S的雷达采样信号分为16路采样频率为250 M/S的信号并行输入给FPGA芯片。然后,在芯片内对这16路信号进行并行处理,完成采样信号与特征库信号的相关计算。首先介绍了快速相关计算的方法和重叠相加法的原理,给出了用FPGA实现快速实时相关计算框图。通过平台测试和仿真计算,结果表明,设计满足资源、时序以及精度等各方面要求。An implementation method about the high-speed real-time radar signal processing IP core is described. The radar signal sampled at 4G/S sampling rate is divided into 16 sampling parallel signals at 250 M/S sampling rate as the FPGA input signals. Then, the 16 signals were processed in parallel in FPGA chip. The processing targets were to complete the related calculations between the radar signal and the characteristic signal. The artical described the method of rapid related calculation and the principle of overlap - add and gave out the fast real time related calculation diagram. By platform testing and the Simulation Calculating, the results show that the design met the resource, timing and precision requirements in all aspects.

关 键 词：FPGA 并行处理 实时相关计算 重叠相加法 雷迭 

分 类 号：TN957.51[电子电信—信号与信息处理]