一种10位电容电阻混合型双极性D/A转换器  

Design of a 10-bit CMOS Capacitive and Resistive Bipolar D/A Converter

作　　者：安超群[1] 彭伟娣[1] 谢晶[1] 曾以成[1] 金湘亮[1] 

机构地区：[1]湘潭大学材料与光电物理学院,湖南湘潭411105

出　　处：《固体电子学研究与进展》2012年第2期198-202,共5页Research & Progress of SSE

基　　金：中国科学技术部国家重大科技资助项目(20112x05008-005-04-02);国家自然科学基金资助项目(60972147);湖南省自然科学基金重点项目(11JJ2036);湖南省教育厅科研基金资助项目(11A116)

摘　　要：在加速度计中,需要数模转换器(DAC)提供一个稳定的偏压来消除重力加速度,要求DAC具有高精度、单调性和小面积等特性。为了解决传统电阻型DAC存在的大面积和传统电容DAC中存在的非单调性等问题,提出了一种电容电阻混合型DAC结构,并设计了一个10位的DAC,用于提供稳定偏压。提出一种新的电容共质心的版图布局,提高了DAC的精度。该DAC在0.5μm CMOS工艺上得以验证实现,微分非线性误差(DNL)最大为0.50LSB,积分非线性误差(INL)最大为0.82LSB,在5V和-5V的双电源供电条件下,芯片功耗为16mW,完全满足了工程需求。In the design of accelerometer,DAC is needed to provide a stable bias voltage to eliminate the influence of gravitational acceleration.For the certain application,the characters that mainly include high precision DAC,good monotonicity,and small area are required.The traditional resistor DAC and capacitor DAC have the problems of large area and non-monotony,respectively.In order to solve the problems above and meet the demands of the application,a combined resistive and capacitive DAC structure is proposed here.A 10 bit proposed architecture DAC which is used to provide a stable bias voltage for accelerometer is implemented and verified in 0.5 μm CMOS technology as well.A unique common centroid layout is used in the capacitor network to reduce the effect of thermal or process linear gradients.The simulation results are as follows,the maximum differential nonlinearity（DNL） of the DAC is 0.50 LSB,the maximum integral nonlinearity（INL） is 0.82 LSB.Under the condition of a dual 5 V and-5 V power supply,power consumption is 16 mW.It can be seen from the simulation results that the proposed DAC can meet the engineering requirements well.

关 键 词：D/A转换器 电阻网络 电容网络 小面积 单调性 双极性 

分 类 号：TN792[电子电信—电路与系统]