独立前向滑块式超高速Viterbi译码器结构设计  

Structural design of high-speed independent forward sliding-block Viterbi decoders

作　　者：高波[1] 肖振宇[1] 张昌明[1] 金德鹏[1] 苏厉[1] 曾烈光[1] 

机构地区：[1]清华大学电子工程系,微波与数字通信技术国家重点实验室,北京100084

出　　处：《清华大学学报（自然科学版）》2012年第3期416-420,共5页Journal of Tsinghua University(Science and Technology)

基　　金：国家“八六三”高技术发展项目(2009AA011205);国家科技重大专项(2009ZX03006-007-02,2011ZX03004-001-01);国家自然科学基金项目(61021001);索尼株式会社系统技术研究所、索尼中国研究院与清华合作项目

摘　　要：超宽带(UWB)通信系统需要高达480Mb/s的Viterbi译码器,而传统并行Viterbi译码器结构难以在现场可编程门阵列(field-programmable gate array,FPGA)上实现该速率。该文提出了独立前向滑块式并行Viterbi译码结构,解决了传统并行Viterbi译码器硬件实现存在的布线拥塞、逻辑资源消耗过大等技术难题,有效提高了系统最大工作时钟频率;同时,给出一种精简加比选单元(ACSU),通过减少加比选迭代运算阶数,降低了关键路径延时,进一步提高了系统最大工作时钟频率。完成4路并行Viterbi译码器的硬件设计,并在Xilinx Virtex-4FPGA上进行了验证,其最高译码速率达720Mb/s。Ultra-wideband(UWB) communication systems require Viterbi decoders with throughputs of up to 480 Mb/s,which cannot be accomplished in field-programmable gate array(FPGA) devices employing traditional parallel structures.A forward independent sliding-block structure was developed for Viterbi decoders to reduce the routing congestion and excessive consumption of logical resources in traditional structures,to achieve a higher maximum operating clock frequency.A simplified add-compare select unit(ACSU) using less iterations is used with a shorter critical path,which further increases the maximum operating clock frequency.A four-fold parallel Viterbi decoder has been implemented in a Xilinx Virtex-4 FPGA device with a maximum decoding rate of 720 Mb/s.

关 键 词：独立前向滑块 VITERBI译码器 超宽带 加比选单元 

分 类 号：TN403[电子电信—微电子学与固体电子学]