基于FPGA视频图像的Canny算法加速器的设计  

Design of FPGA-based Canny algorithm accelerator for video images

作　　者：肖国尧[1] 曲仕茹[1] 

机构地区：[1]西北工业大学自动化学院,陕西西安710072

出　　处：《现代电子技术》2012年第9期91-94,共4页Modern Electronics Technique

摘　　要：由于Canny算法自身的复杂性,使得其做边缘检测的处理时间较长。针对这个问题,提出和实现了一种Canny算法的硬件加速功能。加速功能的设计是以FPGA为硬件基础,并采用了流水线技术来对系统的结构改进和优化。最后通过对有加速器和无加速器的系统分别做图像处理,并对统计时间对比分析。结果表明经过加速改进的系统相对节约了处理时间,并能实时高效地处理复杂图像的边缘。Due to the high complexity of its own,the Canny algorithm requires a long time for edge detection.To solve this problem,this paper proposed and implemented an accelerator of Canny algorithm for edge detection of videos.The accelerator was FPGA-based and adopted a pipelined technology for the improvement of edge detection system.Based on the same input images,the paper compared the average time costs of both systems with/without the accelerator for edge detection.The results show the superior efficiency of the accelerated system on detection of complex edges.

关 键 词：CANNY算子 边缘检测 加速器 现场可编程门阵列 

分 类 号：TN791[电子电信—电路与系统]