基于Virtex-4的DCM动态重配置设计  

DCM Dynamic Reconfiguration Design Based on Virtex-4

作　　者：方火能[1] 邢开宇[1] 曹晓曼[1] 

机构地区：[1]西安电子科技大学电子工程学院,陕西西安710071

出　　处：《电子科技》2012年第5期108-110,114,共4页Electronic Science and Technology

摘　　要：介绍了Xilinx FPGA中DCM的结构和相关特性,提出了一种基于Xilinx FPGA的DCM动态重配置的原理方法,并给出了一个具体的实现系统。系统仅通过外部和Xilinx XC4VFX100相连的少数控制线,就可以在输入100 MHz时钟源的条件下,对DCM进行50～300 MHz范围内准确、快速地变频。本设计系统具有接口简单、实时性强、稳定性高等特点,目前已成功应用到某星载系统中。This paper introduces the structure and related characteristics of Digital Clock Manager（DCM） in Xilinx FPGA,proposes a scheme reconfiguring the DCM dynamically based on Xilinx FPGA,and gives the specific implementation system.With just a few external control signal lines connected to Xilinx XC4VFX100,this system can enable DCM to change frequency accurately and quickly between 50 MHz and 300 MHz under the 100 MHz input clock source conditions.This design system features a simple interface,real time and high stability,and has already been applied to some satellite system successfully.

关 键 词：DCM动态重配置 XILINX VIRTEX-4 时钟源 

分 类 号：TP311.53[自动化与计算机技术—计算机软件与理论]