高性能BLAKE算法研究及其FPGA实现  

Research of high-performance BLAKE algorithm on FPGA platform

作　　者：许文龙[1] 王奕[1,2] 陈佐[1,2] 李仁发[1,2] 宋倩[1] 

机构地区：[1]湖南大学嵌入式系统及网络实验室,长沙410082 [2]湖南大学网络与信息安全湖南省重点实验室,长沙410082

出　　处：《计算机应用研究》2012年第6期2098-2101,共4页Application Research of Computers

基　　金：国家自然科学基金资助项目(60873074;60673061);长沙市科技计划资助项目(K1003028-11);中央高校基本科研业务费资助项目

摘　　要：BLAKE算法是基于ChaCha流密码和采用标准HAIFA迭代模式的SHA-3候选算法之一。针对现有BLAKE算法对于循环单元中G函数模型的研究少,且没有考虑硬件代价及实现结果等问题,提出可重构的设计思想,在FPGA上实现了BLAKE算法循环单元的三种G函数模式。在Xilinx Virtex-5 FPGA上的实现结果表明,在不影响性能的前提下,本方案可重构后的面积比分别实现的面积总和减少了58%。BLAKE algorithm is one of SHA-3 finalist which is based on ChaCha and take use of standard HAIFA iterative mode.Previous research work had been done on hardware implementation of BLAKE algorithm,but the disadvantage of their implementations lay on few research on the G_function module of the round unit of BLAKE without considering hardware costs and results.In order to resolve the above shortage,this paper proposed a new reconfigurable architecture which could support three different parameters of G-function module of round unit of BLAKE algorithms on Xilinx Virtex-5 FPGA.The experimental results show that the proposed design has smaller size that is 58% smaller than others without affecting performance.

关 键 词：安全哈希算法 可重构 现场可编程门阵列 G函数 BLAKE 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]