采用状态度量抽取和内插策略的低功耗Turbo译码器  

Low power Turbo decoder based on the state metric decimation and interpolation strategy

作　　者：李晓峰[1] 冯大政[1] 胡树楷[2] 

机构地区：[1]西安电子科技大学雷达信号处理国家重点实验室,陕西西安710071 [2]西安电子科技大学综合业务网理论及关键技术国家重点实验室,陕西西安710071

出　　处：《西安电子科技大学学报》2012年第3期58-62,71,共6页Journal of Xidian University

基　　金：国家自然科学基金资助项目(60971111);国家重点基础研究发展计划(973)资助项目(2010CB328300)

摘　　要：针对采用最大后验概率算法的Turbo译码器,提出了一种新颖的前向、后向度量计算和存储器管理的策略.通过在前向状态度量计算时对部分度量值等间隔抽取存储,然后在对数似然比计算时经过内插还原出未存储的状态度量值,极大地减少了状态度量存储单元,从而降低了功耗和实现面积.与传统的实现方法比较,当滑窗为128时,可以节省80%的状态度量存储单元.在65nm的工艺下,约束工作电压为1.18V和时钟频率为350MHz时,该方法实现的HSDPA Turbo译码器可以达到21.4Mbit/s的吞吐量和29.3mW的功耗,且每次迭代的能量效率仅为0.171nJ/bit.A novel forward and backword state metric calculation and the memory management strategy are presencted for the turbo decoder which adopts the Log-MAP（Maximum A-Posteriori） algorithm. By the way of decimating the forward state metric first and then interpolating in the LLR（Log Likelihood Ratio） computation stage to reduce the state metric memory size, which acquires significant power and area benefit with ignorable computation penalty. And the soft in soft out（SISO） scheduling and control mechanism are also addressed for supporting our proposed optimization architecture. Compared with the conventional memory management strategy our design could reduce the state metric size by 80 % with the sliding window 128. Based on our proposed architecture an HSDPA turbo decoder is realized by the 65 nm CMOS standard cell library with the frequency of 350 MHz and the voltage of 1.18 V. The result achieves 21.4 Mbit/s throughput and 29.3 mW power consumption, and an energy efficiency of up to 0. 171 nJ/bit/iteration.

关 键 词：TURBO码 最大后验概率译码器 状态度量抽取和内插 超大规模集成电路 

分 类 号：TN911.22[电子电信—通信与信息系统]