CAVLC熵编码器的FPGA高效实现  

Efficient implementation of the CAVLC entropy encoder based on FPGA

作　　者：初秀琴[1] 吴硕[1] 常方[1] 贺文卿[1] 

机构地区：[1]西安电子科技大学电路CAD研究所,陕西西安710071

出　　处：《西安电子科技大学学报》2012年第3期100-105,共6页Journal of Xidian University

基　　金：中央高校基本科研业务费专项资金资助项目(K50510020016);陕西省科技计划资助项目(2011K06-38)

摘　　要：针对H.264标准中基于上下文自适应可变长编码(CAVLC)算法运算复杂度高、不易于实时实现的问题,提出了CAVLC熵编码算法的高效实现体系结构.该设计实现了对宏块数据经分解后的块流中不同类型数据块的编码,克服了传统方案中只能处理一种类型数据块的局限;提出在上游模块采用逆锯齿扫描替代锯齿扫描以省去逆序操作,在不增加上游模块运算量的同时提高了CAVLC模块的效率.现场可编程门阵列(FPGA)验证结果表明,该体系结构的编码系统时钟可达147.78MHz,编码的首次延迟为32个时钟周期,吞吐延迟为16个时钟周期,可以满足高清、实时应用的编码要求.Since the Context based Adaptive Variable Length Coding （CAVLC）algorithm in H. 264 has both high complexity in computation and great difficulty in real-time implementation, a high efficient architecture for this algorithm is presented. In this design, realization of encoding on different types of data blocks in the block stream sourced from the decomposition of a macro block data conquers the limitation in conventional schemes where only one type of data blocks can be processed. Replacement of zig zag scan for reverse zig zag scan in the upstream module results in the elimination of reverse operation and a great rise in efficiency of the CAVLC module with no increase of computation in the upstream module. Finally, results of its verification and realization on FPGA indicate that this structure has as high a maximum coding system frequency as 147.78 MHz, the first coding delay of 32 clock cycles, and a throughput delay of 16 clock cycles, thus adequately meeting the requirement for high-definition and real-time applications.

关 键 词：H.264 CAVLC 熵编码器 FPGA实现 

分 类 号：TN919.8[电子电信—通信与信息系统]