基于Verilog HDL语言的CAN总线控制器设计及验证  

Design and confirmation of CAN bus controller based on Verilog HDL

作　　者：许莉娅[1] 段帅君[2] 李传南[2] 

机构地区：[1]黎明职业大学机电工程系,福建泉州362000 [2]吉林大学电子科学与工程学院,吉林长春130012

出　　处：《现代电子技术》2012年第10期43-46,共4页Modern Electronics Technique

摘　　要：在此利用Verilog HDL设计了一款CAN总线控制器,首先根据协议把整个CAN总线控制器划分为接口逻辑管理、寄存器逻辑和CAN核心模块3个模块,然后用Verilog HDL硬件描述语言设计了各个功能模块,并使用Modelsim软件对各个模块的功能进行了仿真,最后使用FPGA芯片对设计的CAN总线控制器验证,并连接了一个包含该FPGA CAN总线控制器的4节点CAN总线网络。测试结果表明所设计的CAN总线控制器能够完成设定的功能。One type of CAN bus controller was designed with Verilog HDL and tested by the aid of a Cyclone FPGA chip.This CAN bus controller was divided into three functional modules： interface management logic module,register module and CAN core module.Every module was designed with Verilog HDL according to their functions.The functions of these modules were simulated by means of the software Modelsim.The CAN bus controller was verified by FPGA chip,and tested together with a four-node CAN network.The testing results show that the CAN bus controller can implement the required functions.

关 键 词：CAN总线 控制器 FPGA VERILOG HDL 

分 类 号：TN919-34[电子电信—通信与信息系统] TP336[电子电信—信息与通信工程]