基于FPGA的增量式编码器接口电路设计在ARM上的应用  

Application of Incremental Encoder Interface Circuit Design based on FPGA to the ARM

作　　者：武崴 邢庆敏 邵丽颖[2] 杨帆[3] 

机构地区：[1]长春机械科学研究院有限公司,吉林长春130012 [2]空军航空大学航空机械工程系,吉林长春130022 [3]吉林农业大学发展学院,吉林长春130022

出　　处：《工程与试验》2012年第1期48-50,共3页Engineering and Test

摘　　要：应用VHDL硬件描述语言对增量式编码器接口电路进行设计,该电路实现了光电编码器的四倍频、双向计数的功能以及与ARM的接口定义,并在Quartus II环境下给出了VHDL的时序仿真结果。通过Quartus II软件的在线逻辑分析仪实时采集ARM与FPGA通信时的信号值,从而验证设计的可行性。The hardware description language VHDL is applied to design the incremental encoder interface circuit in this paper.The four times frequency,the two-way count function and the ARM interface definition of the encoder can be realized by the circuit.The sequential simulation results of VHDL are given in the Quartus II.The real-time signal values generated when ARM communicated with FPGA are acquired by the online logical analyzer of the Quartus II,which verify the feasibility of the design.

关 键 词：增量式编码器 四倍频 VHDL Quartus II 

分 类 号：TN762[电子电信—电路与系统]