可编程FIR滤波器的FPGA实现  

The Realization of Programmable FIR Filter on FPGA

作　　者：谢海霞[1] 孙志雄[1] 

机构地区：[1]琼州学院电子信息工程学院

出　　处：《电子器件》2012年第2期232-235,共4页Chinese Journal of Electron Devices

基　　金：海南省自然科学基金项目(611133);三亚市院地科技合作项目(2010YD33);三亚市院地科技合作项目(2011YD03)

摘　　要：介绍了FIR滤波器的基本的线性相位结构及FIR滤波器的抽头系数SD算法编码。给定滤波器的数字指标,用MATLB设计抽头系数,最后用Verilog HDL语言实现了一个16阶的FIR低通滤波器并在QuartusⅡ上仿真,并对仿真结果与理论值进行比较,波形仿真结果和理论值相吻和,最后将编程数据文件下载到FPGA芯片上。对于不同性能的FIR滤波器,抽头系数是变化的,因此只要对本设计的抽头系数重新在线配置,就可以实现不同的FIR滤波器。The paper introduced an architecture of linear phase FIR filter and SD coding algorithm of FIR filter coefficients,gave a digital filter index,and then tap coefficients were gained by MATLAB,finally the 16 order low-pass filter was achieved by using Verilog HDL language and simulating on Quartus Ⅱ.The results of waveform simulation and the theoretical value met each other by making a comparison between them.And the programming data files are downloaded to FPGA chip at the last.For the performance of different FIR filter,the tap coefficients were changed,therefore the design of the tap coefficients were online reconfigured,that the different FIR filters were achieved.

关 键 词：FIR滤波器 FPGA QuartusⅡ VERILOG HDL 

分 类 号：TN911.72[电子电信—通信与信息系统]