基于外壳架构与测试访问机制的数字芯核可测试性设计  

Design for Testability of Digital Cores Based on Wrapper and TAM

作　　者：陈圣俭[1] 李广进[1] 高华[1] 

机构地区：[1]装甲兵工程学院控制工程系,北京100072

出　　处：《微电子学与计算机》2012年第6期42-45,50,共5页Microelectronics & Computer

基　　金：国家自然科学基金资助项目(61179001)

摘　　要：深亚徽米技术的应用以及芯核的嵌入性特点.使传统的测试方法不再能满足芯核测试的需要.IEEEStdl 500针对此问题提出了芯核的可测试性设计方案——外壳架构和测试访问机制.基于IEEE Stdl 500.以74373与741 38软梭为例,提出数字芯梭可测试性设计的方法,并通过多种指令仿真验证了设计的合理性;设计的TAM控制器复用JTAC-端口,节约了测试端口资源.提供了测试效率.Because of the development of deep submicron manufacture technology and embeddability of cores, conventional methods cannot apply to cores. To solve this problem, a novel test method which consists of wrapper architecture and test access mechanism is presented by IEEE Stdl500. Taking 74373 and 74138 for example, the design process which is based on IEEE Std1500 is described in detail. Through of multi instruction simulation, the design＇s validity is proved.

关 键 词：IEEE Std1500 外壳 可测试性 测试访问机制 TAM控制器 

分 类 号：TP391.76[自动化与计算机技术—计算机应用技术]