基于FPGA的PUSCH信道估计仿真与实现  

Simulation and realization of channel estimation and in TD-LTE system based on FPGA

作　　者：董宏成[1] 步清明[1] 李小文[1] 施流伟[1] 

机构地区：[1]重庆邮电大学通信与信息工程学院,重庆400065

出　　处：《电子技术应用》2012年第6期51-53,共3页Application of Electronic Technique

基　　金：国家科技重大专项基金资助项(2009ZX3002-009)

摘　　要：基于最小平方(LS)算法,利用FPGA实现了一种适用于TD-LTE系统的上行信道估计算法。主要研究了如何利用FPGA实现LS算法,包括算法的介绍、方案的形成、FPGA实现的处理流程、FPGA实现结果及分析。以Virtex-5芯片为硬件平台,完成了仿真、综合、板级验证等工作。实现结果表明,该信道估计算法应用到TD-LTE系统具有良好的稳定性和可行性。Based on the Least Square （LS） algorithm, a novel uplink channel estimation algorithm in TD-LTE system is im- proved and realized by FPGA. This paper studies the implementation of uplink channel estimation based on FPGA. It includes in- troduction of the algorithm, projects completing, dispose process of FPGA implementation and analysis of FPGA implementation. Then it finishes simulation, synthesis and verification of the board on Virtex-5.Implementation results show that this channel estima- tion algorithm have a very good feasibility and stability in TD-LTE system.

关 键 词：FPGA实现 TD—LTE系统 信道估计 LS算法 VIRTEX-5 

分 类 号：TN929.5[电子电信—通信与信息系统]